Systemverilog

Active-HDL  v.8. 3. 2026

Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator.

• Category: Multimedia & Graphic Design
• Developer: Aldec - Download - Free

• fpga - asic - electronic - design - verification

Doxverilog  v.2.6

Doxverilog is a nativ Verilog/SystemVerilog parser for the Doxygen documentation generator.

• Category: Programming
• Developer: doxverilog.berlios.de - Download - Free

HDL Designer  v.2006.1

HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) an

• Category: Business
• Developer: Mentor Graphics - Download - Price: -

• reuse - rtl - hdl - code - rtl quality

Aldec ALINT SR1  v.2010.10

ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage.

• Category: Utilities
• Developer: Aldec, Inc. - Download - Price: -

• fpga - asic - electronic - design - verification

HDLObf  v.1.0

HDLObf is intended to be a HDL Obfuscator and identifier name change utility.

• Category: Science
• Developer: hdlobf.sourceforge.net - Download - Free